Link: project page
Data compression is essential to large-scale data centers to save both storage and network bandwidth. Current software based method suffers from high computational cost with limited performance. In this project, we are migrating the fundamental workload of the computer system to FPGA accelerator, aiming high throughput performance and high energy efficiency, as well as freeing some CPU resources.
Status: Past Year: 2011 The object of this project was to develop an accurate and fast 6 degree-of-freedom camera tracking system using only natural features. Based on reconstructed sparse 3d structures, we figured out pose of the camera out of matched 3D-2D correspondences. Same kind of point descriptor was used in 3d reconstrunction and online feature extraction to match points. To acheive real-time virtual object augrmentation, we acclerated some parts of the algorithm, feature extraction and apporixate nearest neighbor search, using graphic processing unit. As a result, got over 25fps performance with fairly accurate camera pose estimation for small workspace, which can be used as a test bench for further augmented reality system.
Status: Past Year: 2010-2011 The programmable vector processor design in BONE-V3 was shipped to a major automobile company for their future vehicle SoC platform. The vector processor was tailored to accelerate automobile environment based vision processing such as Forward Collision Warning System (FCWS) and Lane Departure Warning System (LDWS).
Status: Past, On-going at KAIST Year: 2006-2010 BONE is the abbreviation of Basic On-Chip Network, which is an ealrier research on Network-on-Chip (NoC) at KAIST, while BONE-V refers the series of application processor using the developed NoC as communication back-bone in multi-core environment. The goal of this project was to design energy efficient system-on-a-chip architectures and circuits for real-time object recognition applications. From 2006 to 2008, I was involved in the project as a block-level designer. I designed a low-energy microprocessor and special-purposed memory for the first prototype of the series called BONE-V1 after, and a database searching accelerator as a key component for BONE-V2. Then, I led entire SoC design of BONE-V3, the third generation of the series, having over 30 million transistors with 5 heterogeneous cores in mixed domain, which resulted in under 500mW power consumption with the highest energy efficiency per image at the time. The chip was announced at IEEE International Solid State Circuits Conference (ISSCC) 2009, which is a premier conference in solid-state circuits, and its ARM-based embedded system with fabricated SoC won Design Automation Conference (DAC) student design contest in 2010. Please see publication section for details of the SoC.